5,565 research outputs found

    Embedded minimal ends asymptotic to the helicoid

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    The ends of a complete embedded minimal surface of {\em finite total curvature} are well understood (every such end is asymptotic to a catenoid or to a plane). We give a similar characterization for a large class of ends of {\em infinite total curvature}, showing that each such end is asymptotic to a helicoid. The result applies, in particular, to the genus one helicoid and implies that it is embedded outside of a compact set in R3{\mathbb R}^3

    Ion mass spectrometer experiment for ISIS-2 spacecraft

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    The International Satellite for Ionospheric Studies (ISIS) program of NASA was the longest duration program in NASA history. A number of satellites were flown under this program, the last being called ISIS-2, which was launched on April 1, 1971 and operated successfully for over 13 years. An experiment called the Ion Mass Spectrometer (IMS) was flown on the ISIS-2 spacecraft. It operated for 10 years providing a large data base of positive ion composition and ion flow velocities along the orbit of the satellite, the latter being circular at 1400 km with a 90 degree inclination. The data were processed and reside in the National Space Sciences Data Center

    Development of a miniature mass analyzer and associated instrumentation for improved capabilities in the analysis of low energy plasmas from a rocket or satellite platform

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    The University of Texas at Dallas (UTD) Center for Space Sciences (CSS) has designed, developed, and fabricated three miniature mass spectrometers and their associated instrumentation in fulfillment of a NASA contract. The ion mass spectrometer analyzers furnished under this contract were modeled after a unit developed during a previous NASA grant. Three assemblies are described: (1) the magnetic sector; (2) the ion detector; and (3) the amplifier and power supply

    A Dynamically Reconfigurable Parallel Processing Framework with Application to High-Performance Video Processing

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    Digital video processing demands have and will continue to grow at unprecedented rates. Growth comes from ever increasing volume of data, demand for higher resolution, higher frame rates, and the need for high capacity communications. Moreover, economic realities force continued reductions in size, weight and power requirements. The ever-changing needs and complexities associated with effective video processing systems leads to the consideration of dynamically reconfigurable systems. The goal of this dissertation research was to develop and demonstrate the viability of integrated parallel processing system that effectively and efficiently apply pre-optimized hardware cores for processing video streamed data. Digital video is decomposed into packets which are then distributed over a group of parallel video processing cores. Real time processing requires an effective task scheduler that distributes video packets efficiently to any of the reconfigurable distributed processing nodes across the framework, with the nodes running on FPGA reconfigurable logic in an inherently Virtual\u27 mode. The developed framework, coupled with the use of hardware techniques for dynamic processing optimization achieves an optimal cost/power/performance realization for video processing applications. The system is evaluated by testing processor utilization relative to I/O bandwidth and algorithm latency using a separable 2-D FIR filtering system, and a dynamic pixel processor. For these applications, the system can achieve performance of hundreds of 640x480 video frames per second across an eight lane Gen I PCIe bus. Overall, optimal performance is achieved in the sense that video data is processed at the maximum possible rate that can be streamed through the processing cores. This performance, coupled with inherent ability to dynamically add new algorithms to the described dynamically reconfigurable distributed processing framework, creates new opportunities for realizable and economic hardware virtualization.\u2

    High-speed dynamic partial reconfiguration for field programmable gate arrays

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    With dynamically and partially reconfigurable designs, it is necessary that the speed of the reconfiguration be accomplished in a time that is sufficiently small such that the operation of reconfiguration is not the limiting factor in the process. Therefore, the communication between the source of configuration and the configurable unit must be made as fast as possible. The aim of this work is to use an embedded controller internal to the FPGA to control the reconfiguration process and obtain the maximum speed at which reconfiguration can occur, with current FPGA technology. The use of Direct Memory Access (DMA) driven operations instead of the current arbitrated bus architectures yielded a 30% increase in the speed of reconfiguration compared to other methods such as OPB_HWICAP and PLB_HWICAP [1]. The use of interrupt driven partial reconfiguration was also introduced, allowing the processor to switch to other tasks during the reconfiguration operation. All of these contributions lead to significant performance improvements over current partial reconfiguration subsystems. The configuration controller was tested using four partially reconfigurable system implementations: (i) one targeting the Hard IP PowerPC405 on Virtex-4, (ii) a second targeting the Soft IP MicroBlaze on Virtex-5, (iii) a third targeting the Hard IP PowerPC440 on Virtex-5, and (iv) a fourth system targets the Hard IP PowerPC440 on Virtex-5 capable of adaptive feedback. The adaptive feedback Virtex-5 system can use internal voltage and temperature measurements from the Xilinx System Monitor IP to dynamically increase or decrease the speed of reconfiguration and/or change other reconfigurable aspects of the system to better match the environment

    Self-Directed Work Team Transition: Leadership Influence Mediates Self Determination Theory to Describe Variation in Employee Commitment

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    Self-Directed Work Teams (SDWT) are strategic organization designs based on the belief that the time required to make good decisions decreases when employees are empowered to tap their tacit job knowledge. Because this strategy requires employees to think differently about the way they perform their jobs, the supervisor plays a critical role in SDWT implementations. If leaders fail to adequately manage the challenges associated with the transition to the SDWT structure, employee commitment towards the team and organization at large may suffer, putting the realization of SDWT benefits at risk. To better understand this complicated process, this research describes a field study observation designed to explore the relationship between the constructs of Self-Determination Theory (autonomy, competence, relatedness) with employee affective commitment towards a SDWT transition. Additionally, this research evaluates the mediating role leadership influence tactics has on the relationship between Self-Determination Theory and employee affective commitment towards a SDWT transition
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